PCB Antenna Design Tutorial: NFC Antenna Layout Best Practices

You've calculated your antenna inductance, picked your matching capacitors, and the math all checks out. Now comes the part where most NFC designs fail: the PCB layout.

A perfectly calculated antenna with a bad layout will underperform a rough design with a good layout. This tutorial covers the specific PCB layout techniques that separate working NFC antennas from expensive paperweights.

PCB Antenna Layout Fundamentals

Why PCB Layout Matters for Antennas

A PCB antenna isn't a normal trace. Every layout decision affects its electrical behavior:

• Trace width → resistance → Q-factor → read range
• Trace spacing → parasitic capacitance → self-resonant frequency
• Ground plane proximity → eddy current losses → massive performance reduction
• Via placement → added inductance and resistance at transitions
• Component placement → parasitic coupling → detuning

In digital PCB design, you can often get away with "close enough." In antenna design, 0.1mm of trace width variation or 1mm of ground plane encroachment can shift your resonant frequency by hundreds of kHz and cut your read range in half.

Anatomy of a PCB NFC Antenna

A typical NFC PCB antenna consists of:

┌─────────────────────────────────────┐
│  ┌───────────────────────────────┐  │  ← Outer turn (turn 1)
│  │  ┌─────────────────────────┐  │  │  ← Turn 2
│  │  │  ┌───────────────────┐  │  │  │  ← Turn 3
│  │  │  │  ┌─────────────┐  │  │  │  │  ← Turn 4 (inner)
│  │  │  │  │             │  │  │  │  │
│  │  │  │  │  KEEP-OUT   │  │  │  │  │  ← No copper zone
│  │  │  │  │   ZONE      │  │  │  │  │
│  │  │  │  └──────┐      │  │  │  │  │
│  │  │  └─────────┤      │  │  │  │  │  ← Inner terminal
│  │  └────────────┤      │  │  │  │  │     (via to bottom layer
│  └───────────────┤      │  │  │  │  │      for routing out)
└──────────────────┤      │  │  │  │  │
                   │  IC  │  │  │  │  │  ← NFC IC + matching
                   └──────┘  │  │  │  │     components nearby
                             ...

The spiral starts at the outer edge, winds inward, and the inner terminal connects to the bottom layer via a via to route back to the IC without crossing the antenna traces.

Step-by-Step PCB Layout Process

Step 1: Define the Antenna Area

Before placing a single trace, define your antenna boundary:

1. Outer dimensions — determined by your enclosure and read range requirements. Larger antenna = more captured flux = better range. Typical sizes:

   • Credit card format: 80mm × 50mm (maximum range)
   • Smartphone-sized: 40mm × 40mm (good range)
   • Wearable/IoT: 20mm × 15mm (short range, challenging)

2. Ground plane clearance — extend the keep-out zone at least 1mm beyond the outermost antenna trace on all sides. This is non-negotiable.

3. Component keep-out — no components taller than 1mm within the antenna loop area (they can detune the antenna or block the magnetic field).

Step 2: Set Up Layer Stackup

For a standard 2-layer PCB:

For a 4-layer PCB:

Critical rule for multi-layer boards: Cut a window in ALL inner ground/power planes directly under and around the antenna. Any continuous copper under the antenna acts as a shorted turn and will dramatically reduce inductance and Q-factor.

Step 3: Route the Antenna Spiral

Trace Width Selection

Wider traces have lower DC and AC resistance (skin effect is significant at 13.56 MHz — skin depth in copper ≈ 18 µm). Lower resistance means higher Q-factor and better read range.

Trace Spacing

Minimum 0.2mm between turns. Recommended 0.3–0.5mm.

Tighter spacing = more turns in a given area = more inductance. But tighter spacing also increases inter-turn parasitic capacitance, which lowers the self-resonant frequency (SRF). If SRF drops near 13.56 MHz, the antenna becomes unusable.

Rule of thumb: Keep spacing ≥ trace width for the best inductance-to-capacitance ratio.

Corner Style

• 90° corners: Acceptable for NFC frequencies. The "no right angles" rule from microwave PCB design doesn't apply at 13.56 MHz — the wavelength is 22 meters.
• 45° chamfered corners: Slightly better current distribution. Use if your EDA tool supports it easily.
• Rounded corners: Marginal improvement. Not worth the layout effort unless your CAD generates them automatically.

Step 4: Route the Inner Terminal

The inner end of the spiral needs to connect back to the IC without crossing antenna traces. Two approaches:

Via to bottom layer (recommended):

1. Place a via at the inner terminal
2. Route on the bottom layer back to the IC pads
3. Use another via near the IC to return to the top layer

Via specifications:

• Drill diameter: 0.3mm minimum
• Pad diameter: 0.6mm minimum
• Use 2 vias in parallel for lower resistance if space permits

Crossover bridge (for single-layer or flex):

1. Use a jumper wire or 0Ω resistor to bridge over one antenna trace
2. Less ideal than a via — adds resistance and parasitic inductance

Step 5: Place Matching Components

Position matching capacitors and any damping resistor as close to the IC antenna pins as possible:

• Maximum distance from IC to first matching component: 3mm
• Use short, wide traces between IC and matching components — these carry the 13.56 MHz signal
• Ground return path for shunt capacitors must be short and direct — use a via to a ground plane directly under the component

Component orientation:

• Align capacitors parallel to each other to minimize coupling
• Place C_parallel and C_series on the same side of the IC pins for shortest routing

Step 6: Ground Plane Design

This is where most designers make critical mistakes.

DO:

• Remove ALL copper (ground, power, signal) under the antenna spiral area
• Extend the copper-free zone 1–2mm beyond the outermost trace
• Provide a solid ground plane everywhere ELSE on the board
• Connect the ground plane on top and bottom layers with stitching vias around the antenna perimeter

DON'T:

• Leave ground fill under the antenna "because my autorouter put it there"
• Use thermal relief pads that create ground discontinuities near matching components
• Route digital signals under or parallel to the antenna traces

     WRONG                          RIGHT
┌──────────────────┐       ┌──────────────────┐
│▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓│       │▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓│
│▓▓┌──────────┐▓▓▓│       │▓▓┌──────────┐▓▓▓│
│▓▓│ antenna  │▓▓▓│       │▓▓│ antenna  │   ▓│
│▓▓│ ▓▓▓▓▓▓▓ │▓▓▓│       │▓▓│          │   ▓│
│▓▓└──────────┘▓▓▓│       │▓▓└──────────┘   ▓│
│▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓│       │▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓▓│
└──────────────────┘       └──────────────────┘
  Ground under antenna       Ground removed properly
  = shorted turn             = full performance
  = 50-90% range loss

Step 7: EMC Considerations

NFC readers are intentional radiators — they emit at 13.56 MHz by design. But you still need to pass EMC:

• Harmonics: The 2nd and 3rd harmonics (27.12 and 40.68 MHz) must be below limits. Add a low-pass filter on the reader output if needed.
• Shielding: Keep the reader's PA (power amplifier) output away from sensitive analog inputs.
• Cable routing: If the antenna connects via a cable, use shielded twisted pair and add common-mode chokes.

Advanced Layout Techniques

Dual-Layer Antenna

For maximum inductance in minimum space, use both PCB layers:

• Wind the first half of the spiral on the top layer
• Via to the bottom layer at the midpoint
• Continue the spiral on the bottom layer in the same direction

This effectively doubles the number of turns without increasing the antenna area. The trade-off is increased parasitic capacitance between layers (the FR-4 dielectric is thin — 0.2mm for inner layers).

When to use: Small form factors (< 25mm) where you need high inductance but can't increase antenna area.

Antenna on Flex PCB

Flex PCBs enable antenna integration on curved surfaces (wearables, cylindrical products):

• Use polyimide substrate (εr ≈ 3.4)
• Single-layer designs are easier to manufacture on flex
• Minimum bend radius depends on copper thickness — typically 6× the flex thickness
• Account for adhesive layers in inductance calculations (they add dielectric)
• Use the Pro Antenna Designer to calculate inductance for your specific substrate

Split Antenna Design

For products where the antenna must avoid a central feature (camera, display, sensor):

• Split the antenna loop into two connected halves on opposite sides
• Connect with traces routed around the obstruction
• Inductance is reduced vs. a single continuous loop — compensate with additional turns
• Verify coupling symmetry with simulation

DFM: Design for Manufacturing

Panelization

If producing at volume, antenna performance can vary across a panel:

• Inner panels have tighter dimensional control than edge panels
• Specify ±10% copper plating thickness tolerance for antenna traces
• Request electrical test including impedance measurement if your volume justifies it

Solder Paste and Component Placement

• Use solder paste stencil thickness appropriate for your matching component packages (0402: 0.1mm stencil)
• Place matching components on the same side as the IC — no tombstoning risk from reflow thermals
• Matching components must be placed AFTER antenna inductance is verified (order component installation accordingly for rework)

Test Points

Add test points for:

• Antenna terminals (both ends) — for VNA measurement
• Matching network output — between matching components and IC
• Ground — near antenna for probe reference

Place test points outside the antenna loop area to avoid detuning during normal operation.

Exporting Your Design

Once your layout is complete, you need manufacturing files:

1. Gerber files — RS-274X format for all copper, mask, silk, and drill layers
2. Drill file — Excellon format with via specifications
3. Assembly drawing — component placement and polarity
4. BOM — bill of materials with exact capacitor values and tolerances

The Pro Antenna Designer can export antenna geometry that you import into your EDA tool (KiCad, Altium, Eagle) as a starting point, then add your matching components and routing.

Verification Checklist

Before sending your design to manufacturing:

• Ground/power planes removed under antenna area (ALL layers)
• Keep-out zone extends ≥1mm beyond outer antenna trace
• Trace width and spacing match calculated values
• Inner terminal via placed correctly with adequate pad size
• Matching components within 3mm of IC pins
• Ground return path for shunt capacitor is short and direct
• No digital signals routed under or near antenna
• Test points placed outside antenna area
• DRC (Design Rule Check) passes with antenna-specific rules
• Impedance matching values verified with calculator

Conclusion

PCB antenna layout for NFC is where calculation meets craft. The math gives you the right parameters — trace width, spacing, number of turns, matching component values. But translating those parameters into a PCB that actually performs requires attention to ground planes, via placement, component positioning, and manufacturing tolerances.

Use the Pro Antenna Designer to generate your starting geometry, follow the layout guidelines in this tutorial, and always verify with measurement before going to production.

For the underlying theory and calculations, see our NFC Antenna Design Guide and 13.56 MHz Impedance Matching Guide.